Chemical Mechanical Polishing (CMP) utilizes the synergistic effect of chemical etching and mechanical abrasion to achieve nanometer-scale surface control. In wafer manufacturing processes, each deposited metal or dielectric layer typically exhibits surface topography variations. CMP enables planarization to nanometer-level flatness, ensuring the precision of subsequent lithography and etching processes.The technology is widely used for planarization of semiconductor integrated circuits, as well as oxide layers, metal films, and through-silicon via (TSV) structures.

Process/Testing Capabilities

Supported thin film thickness: 50 nm – 2000 nm

Process uniformity: ≈ 5% (excluding 5 mm edge exclusion)

Surface roughness (Ra): SiO₂ < 0.5 nm; Cu < 1 nm

Technical Specifications

Wafer size: 4-inch, 6-inch, and 8-inch

Square samples: 1 × 1 cm, 1.5 × 1.5 cm, 2 × 2 cm, and 3 × 3 cm (for other sizes, please contact process engineer)

Removal rate: > 200 nm/minWafer thickness: > 350 μm

Small sample thickness: > 400 μm