| Model: | RTP-761SA |
|---|---|
| Function: | RTP-761SA |
| Engineer: | Li / +86-21- 34206126-6012 / litq@1 |
| Location: | East Area,Epitaxy/Ion Implantation Zone |
| Equipment ID: | EEI0RTP01 |
Capable of processing 8-inch silicon wafers as well as smaller compatible sample sizes. Enables rapid thermal annealing, heat treatment, and thin oxide growth. Also supports annealing under a hydrogen atmosphere.
Process/Testing Capabilities
Maximum process temperature: up to 1250 °C
Temperature uniformity: ±0.5% above 600 °C; ±3 °C below 600 °C
Temperature repeatability: ±1 °C
Ramp rate: 30 °C/s
RTO (Rapid Thermal Oxidation):
For SiO₂ thickness of 100 Å:
Accuracy: 100 Å ± 5 Å
Repeatability: 3%
Within-wafer non-uniformity: < 5%
RTA (Rapid Thermal Annealing):
Temperature control accuracy: < 2 °C
Temperature uniformity: ±1%
Run-to-run repeatability: < 1%
Technical Specifications
Equipped with an 8-inch SiC wafer susceptor, compatible with 6-inch, 4-inch, 3-inch wafers, as well as smaller samples for thermal processing.Heating source: 33 halogen lamps, each rated at 3 kW.
Temperature measurement:
Below 800 °C: K-type thermocouple
800 °C to 1250 °C: Infrared pyrometer
Gas lines configuration:
N₂: Two lines, with flow ranges of 100 slm and 50 slm, respectively
O₂: One line, 50 sccm
H₂ + PN₂: One line
1. Inert Atmosphere (N₂):
Prevents oxidation of the wafer surface and is suitable for annealing and dopant activation processes.During ion implantation, high-energy ions bombard the semiconductor lattice, causing atomic displacement, lattice distortion, or even amorphization. Rapid Thermal Annealing (RTA) restores crystal integrity by providing sufficient thermal energy for atoms to rearrange into their proper lattice positions.Dopant atoms (e.g., boron, phosphorus, arsenic) must occupy substitutional lattice sites (e.g., silicon sites) to effectively generate charge carriers (holes or electrons). The high-temperature environment of RTA promotes substitutional incorporation, enabling electrical activation.Compared with conventional long-duration annealing, which can lead to excessive dopant diffusion and degradation of device dimensional control (especially for nanoscale devices), RTA employs rapid ramp-up to high temperatures (typically 1000–1200 °C) with very short dwell times (seconds to milliseconds), significantly suppressing diffusion and ensuring precise feature dimensions.
2. Oxidizing Atmosphere (O₂):
Enables the formation of a thin oxide layer during annealing (e.g., post source/drain anneal oxidation for surface protection).
3. Reducing Atmosphere (H₂):
Reduces metal contamination and improves interface properties. This is achieved through reduction reactions, hydrogen termination, and interface passivation, which remove metallic impurities and enhance interface quality. The effectiveness depends on process parameters such as temperature, hydrogen concentration, and annealing time.
During RTA of ion-implanted polysilicon, a mixed gas of N₂ and O₂ with a flow ratio of 4000:1 can be introduced to significantly improve sheet resistance uniformity. Experimental results show that, after conventional N₂ annealing, the sheet resistance distribution ranges from 150–200 Ω/□, whereas under the mixed atmosphere, the variation is reduced to within ±5%.Mechanism:N₂ protects the silicon surface, while a slight oxidation induced by O₂ modulates polysilicon grain boundaries, suppressing abnormal dopant diffusion.
2. Damage Recovery in Power Diode Fabrication:
Dry etching in power diode fabrication can introduce interface defects. An RTA process at 275 °C for 3 minutes under an N₂ atmosphere effectively repairs etch-induced damage, resulting in improved breakdown voltage.Mechanism:As an inert gas, N₂ prevents oxidation at elevated temperatures while providing a suitable environment for lattice atoms to rearrange, repairing amorphized regions caused by ion bombardment.
3. NiSi Silicide Formation Process:
In NiSi silicidation, annealing at 400–450 °C for 1 minute under an N₂ atmosphere promotes the reaction between nickel and silicon to form low-resistivity silicide while preventing metal oxidation. This process is widely used in FinFET gate and interconnect structures to reduce contact resistance.Mechanism:N₂ isolates oxygen and prevents the formation of metal oxide layers, ensuring controlled silicidation reactions.
常规SOAK工艺包括Pre-hit,ramp,soak,cold。本机台可以对温度,升温速率,持温时间,气体通入节点及通入量进行自定义编辑
该设备支持三种气体,分别为O2,N2, Ar&H2混气,其中N+O 可搭配使用,也可以单独使用,Ar+H2 单独使用.