ICP-RIE Deep Silicon Etching System

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Silicon Etcher

Operating

Model：	ICP-SR
Function：	1. Deep silicon etching using Bosch or non-Bosch processes 2. TSV (Through-Silicon Via) deep silicon etching 3. Surface silicon structure etching for SOI wafers
Engineer：	Mr. Liu / +86-21- 34206126-6013 / minliu@1
Location：	West Area, Thin Film II Zone
Equipment ID：	WF2SDSE01

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Basic Equipment Information
Operating Principle
Typical Application Case

Main Application

This system is primarily used for silicon and SOI micro/nanostructure etching. Typical applications include fabrication of nanoscale structures such as silicon waveguides and gratings, as well as deep silicon etching in MEMS devices.

Process / Testing Capabilities

Shallow silicon etching:

Suitable for structures such as gratings and waveguides

Enables nanometer-scale control of etch depth

Deep silicon etching (Bosch process):

High etch rate for silicon

High selectivity to photoresist

High aspect ratio etching capability

Technical Specifications

Shallow silicon etch rate: as low as 2 nm/s, enabling vertical etching profiles
Deep silicon etch rate: up to 4 μm/min. Selectivity to photoresist: >100:1. Aspect ratio: >30:1

The system utilizes alternating etching and passivation steps based on fluorine-based plasma chemistry. Etching gas: SF₆ (provides fluorine radicals for silicon etching). Passivation gas: C₄F₈ (forms fluorocarbon polymer layers on sidewalls). During operation, the process alternates between etching and passivation cycles every 5–10 seconds:

The etching step isotropically removes silicon

The passivation step deposits a protective polymer layer on sidewalls

Ion bombardment in the vertical direction removes the bottom passivation layer, enabling continued downward etching

This cyclic “etch–passivation–etch” mechanism suppresses lateral etching and ensures highly anisotropic, vertical profiles.

Deep trench etching in MEMS device fabrication

Primarily used for deep silicon etching. Metal mask samples are not accepted. Designed for 6-inch wafers; compatible with smaller substrates. Non-standard samples must be mounted onto carrier wafers for processing.

The list below shows FAQs (click a question to view the answer). If your question is not listed, you can leave a message using the link.

FAQs

01

请问该设备可以使用什么掩膜材料？

该设备可接受各种光刻胶掩膜，SiO2或SiNx，各种有机薄膜等，不接受金属掩膜。

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